1. Field of the Invention
This disclosure relates to a semiconductor device, and more particularly to a semiconductor device and method for fabricating the semiconductor device with damascene bit lines that improves the process margin and simplifies the fabrication process.
2. Description of the Related Art
As the size of semiconductor devices decrease, interconnections of the semiconductor devices become finer. Accordingly, etching the interconnection causes many problems. It has become more difficult to assure a process margin for a semiconductor device having a capacitor on a bit line COB structure while simultaneously maintaining the required dielectric properties between a storage node contact and bit line.
FIGS. 1A through 1D are cross sectional diagrams illustrating a method of fabricating a conventional semiconductor device having a Capacitor Over Bit-line (COB) structure.
Referring to FIG. 1A, a field isolation film 105 is formed on a field region of a semiconductor substrate 100, which includes an active region 101, through a conventional shallow trench isolation (STI) process.
A gate 110 having a stacked structure of a gate insulating film 111, a gate electrode material 112, and a capping layer 113 is formed on the semiconductor substrate 100. A spacer 115 is formed on the sidewall of the gate 110. A first interlayer insulating film 120 is formed on the substrate including the gate 110. Contacts 125 are formed to expose portions of the active region 101 through a self aligned contact (SAC) process.
A conductive material, such as a polysilicon film, is deposited on the substrate to fill the contacts 125 and then an etch back or chemical mechanical polishing (CMP) process is performed to form a storage node contact pad 131 and a bitline contact pad 135. At this time, the storage node contact pad 131 and the bitline contact pad 135 are connected to impurity regions (not shown) of a predetermined conductivity type, which are formed in the active region 101.
Next, a second interlayer insulating film 140 is deposited on the first interlayer insulating film 120 and then patterned to form a bit line contact 141 that exposes the bitline contact pad 135 of the contact pads 131 and 135.
Referring to FIG. 1B, a metal film, for example a tungsten film, is deposited on the substrate including the bit line contact 141 and then etched to form a bitline contact plug 145 in the bit line contact 141 through an etch back or a CMP process.
Next, a barrier metal film 161, a conducting material 162 for a bit line, and a capping material 163 for a bit line are sequentially formed on the second interlayer insulating film 140. The capping material 163, the conducting material 162, and the barrier metal film 161 are then etched using a mask (not shown) to form a bit line 160.
Next, a spacer material is deposited on the second interlayer insulating film 140 and the bit line 160 and is then etched to form a bit line spacer 165 on the side wall of the bit line 160.
Referring to FIG. 1C, a third interlayer insulating film 170 is deposited on the second interlayer insulating film 140 as well as the bit line 160, and then the second and third interlayer insulating films 140 and 170 are etched to form a storage node contact 171 exposing the storage node contact pad 131.
Referring to FIG. 1D, a conducting material for a contact plug, for example, a polysilicon film, is deposited on the third interlayer insulating film 170 to fill the storage node contact 171. The conducting material is then etched to form a storage node contact plug 175 in the storage node contact 171 through a CMP or etch back process.
Next, an etching stopper 180 and a mold oxide film (not shown) are deposited on the substrate, and then etched to form an opening (not shown) exposing the storage node contact plug 175. A polysilicon film for a storage node is deposited on the mold oxide film including the opening and then removes the mold oxide film during the CMP process for node separation. As a result, a storage node 190 of a capacitor that is in contact with the storage node contact plug 175 is formed.
As described above, since the conventional method for fabricating the semiconductor device to form bitlines includes depositing and patterning of metal film, the process is very complicated and very difficult. Also, it is difficult to assure the process margin while maintaining the required dielectric properties between a storage node contact and the bit line during the formation of the storage node contact.
Embodiments of the invention address these and other disadvantages of the prior art.